1. Field of the Invention
The present invention relates to etching compositions, and more particularly, the present invention relates to an etching composition having a high etching selectivity, a method of preparing the same, a method of selectively etching an oxide film, and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
Generally, a capacitor in a semiconductor memory device, such as a DRAM or an SRAM, contains a storage electrode, a dielectric film, and a plate electrode. The dielectric film is typically made from a material having a low dielectric constant such as silicon oxide (SiO2), silicon oxide/silicon nitride (SiO2/Si3N4), and the like.
As the degree of integration of memory devices has increased to the gigabit range or more, the useable area per unit cell has decreased to the extent that problems have arisen in manufacturing the memory devices. It is particularly difficult to form a capacitor with a required capacitance of at least 25 μF/cell in the small usuable areas available in highly integrated devices.
Recently, in an effort to produce sufficient capacitance, capacitors have been manufactured to have a cylindrically shaped structure. By employing this structure, both the inner and the outer areas of the capacitor form capacitive regions. In addition, increasing the height of the storage electrode allows for an increase in capacitance without occupying additional surface area. A Hemi-Spherical Grain (HSG) layer may also be formed on the storage electrode to further increase the surface area of the capacitor, thereby further increasing capacitance.
Methods of manufacturing semiconductor memory devices having a capacitor with an HSG silicon layer are disclosed in U.S. Pat. No. 6,413,813 (issued to Jeng Erik) and U.S. Pat. No. 6,403,411 (issued to Chih-Hsun Chu et al.).
Reference is made to FIGS. 1A through 1 D, which are cross-sectional views illustrating a conventional method of manufacturing an HSG capacitor of a semiconductor memory device.
As shown in FIG. 1A, an isolation layer 15 is formed on a substrate 10 to define an active region. Then, gate structures 35 are formed on the active region of the substrate 10. Each of the gate structures 35 includes a gate electrode 20, a capping layer 25, and a spacer 25. Subsequently, source/drain regions 40 are formed by an ion implantation process between the gate structures 35. A conductive layer is deposited on the entire surface of the substrate 10 including the gate structure 35, and then the deposited conductive layer is planarized to form a contact pad 45. An interlayer dielectric (or insulating interlayer) 50 is formed on the substrate 10. The interlayer dielectric 50 is then patterned to form a contact hole to expose the contact pad 45. A conductive layer is deposited on the interlayer dielectric 50 to fill the contact hole. The conductive layer is then planarized to form a storage node contact plug 55, which is connected to the contact pad 45.
Then, as shown In FIG. 1B, an etch stop layer 60 and a lower sacrificial layer 65 are subsequently deposited on the interlayer dielectric 50 and the storage node contact plug 55. The etch stop layer 60 includes a nitride material, and the lower sacrificial layer 65 includes an oxide material such as BPSG.
On the lower sacrificial layer 65, an upper sacrificial layer 70 is formed using an oxide material such as PE-TEOS. The upper sacrificial layer 70, the lower sacrificial layer 65, and the etch stop layer 60 are subsequently etched to form a storage node contact hole 75 to expose the storage node contact plug 55.
Referring to FIG. 1C, a doped polysilicon layer is formed on the exposed storage node contact plug 55, the inner wall portion of the storage node contact hole 75, and the upper sacrificial layer 70. The doped polysilicon layer is then patterned to form a storage electrode 80 on the inner wall portion of the storage node contact hole 75 and the storage node contact plug 55. An HSG silicon layer 85 is then selectively formed on the storage electrode 80.
Then, referring to FIG. 1D, the upper sacrificial layer 70 and the lower sacrificial layer 65 are removed. Generally, this is done by a wet etching process employing an LAL etchant solution. Then, an oxide layer or a nitride layer, and conductive layer are sequentially deposited. The conductive layer, the oxide layer or the nitride layer, and the etch stopping layer 60 are subsequently patterned to form the dielectric film 90 and the upper electrode 95 covering a cell array region on the storage electrode 80, thereby completing an HSG capacitor 97.
The conventional method suffers a drawback in that the polysilicon storage electrode tends to deteriorate during formation of the HSG silicon layer. As a result, the storage electrode is susceptible to damage when the upper and the lower sacrificial layers are removed. This is explained further below.
FIG. 2 is an electron microscope image of a storage electrode after etching of an oxide sacrificial layer using a conventional LAL solution.
As seen in FIG. 2, the polysilicon storage electrode suffers damage (A) when the upper and the lower sacrificial layers are removed. This is because the polysilicon in the storage electrode crystallizes during the heat treatment used to grow the HGS silicon layer. Ammonium fluoride (NH4F) ions, which are contained in the LAL etching solution used to remove the oxide sacrificial layer, readily exfoliates the crystallized polysilicon. Accordingly, damage of the storage electrode is induced.
In an effort to prevent the problems associated with the use of the LAL etching solution, a wet etching method of removing the oxide layer has been developed using an etching solution having hydrogen fluoride and de-ionized water in a mixed ratio of about 5:1.
FIG. 3 is an electron microscope picture of a storage electrode after etching of a sacrificial oxide layer using a 5:1 hydrogen fluoride solution.
Referring to FIG. 3, when the 5:1 hydrogen fluoride solution is used to remove the upper and the lower oxide sacrificial layers, the storage electrode is relatively undamaged when compared with the etching process using the LAL etching solution. However, the amount of etching dispersion on the etch stopping layer located on the substrate increases. Etching dispersion means that the etching was uneven. In addition, the amount of the nitride layer etched also increases, therefore reducing the etching margin when an over-etching occurs.
FIG. 4A is a plan view to explain the thickness (etching) dispersion of the remaining nitride layer after an etching process of a dipping technique using the conventional 5:1 hydrogen fluoride solution. FIG. 4B is a plan view to explain the thickness (etching) dispersion of the remaining nitride layer after an etching process of a circulating technique using the conventional 5:1 hydrogen fluoride solution.
Referring to FIG. 4A, a dipping-type wet etching process was implemented for about 670 seconds. The mean thickness of the nitride layer remaining on the substrate was about 419 Å. The maximum thickness thereof was about 442 Å, and the minimum thickness thereof was about 373 Å. That is, the difference between the maximum thickness and the minimum thickness of the nitride layer was about 69 Å. Therefore, it can be concluded that the wet etching process was non-uniform for the nitride layer.
Referring to FIG. 4B, a circulating-type wet etching process was implemented for about 750 seconds. The mean thickness of the nitride layer remaining on the substrate was about 405 Å. The maximum thickness thereof was about 444 Å, and the minimum thickness thereof was about 405 Å. That is, the difference between the maximum thickness and the minimum thickness of the remaining nitride layer was about 39 Å. The difference was greatly reduced compared with the dipping-type wet etching, but the wet etching process was still non-uniform for the nitride layer.
The pH of 5:1 hydrogen fluoride solution is about 1, i.e., strongly acidic. Therefore, the wet etching process is performed under a strong acid atmosphere. As a result, the nitride layer is non-uniformly etched and the dispersion of the nitride layer is high. In addition, particles exfoliated from a sloped portion or the back portion of the substrate may be adsorbed onto the surface portion of the substrate during the wet etching process so as to induce a reflow-type defect.